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NXP Semiconductors /MIMXRT1021 /FLEXRAM /TCM_CTRL

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Interpret as TCM_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TCM_WWAIT_EN_0)TCM_WWAIT_EN 0 (TCM_RWAIT_EN_0)TCM_RWAIT_EN 0 (FORCE_CLK_ON)FORCE_CLK_ON

TCM_RWAIT_EN=TCM_RWAIT_EN_0, TCM_WWAIT_EN=TCM_WWAIT_EN_0

Description

TCM CRTL Register

Fields

TCM_WWAIT_EN

TCM Write Wait Mode Enable

0 (TCM_WWAIT_EN_0): TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.

1 (TCM_WWAIT_EN_1): TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
TCM_RWAIT_EN

TCM Read Wait Mode Enable

0 (TCM_RWAIT_EN_0): TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.

1 (TCM_RWAIT_EN_1): TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
FORCE_CLK_ON

Force RAM Clock Always On

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data